dcr1910v85 phase control thyristor preliminary information ds5878-1.4 june 2008 (ln26212) 1/10 www.dynexsemi.com features double side cooling high surge capability applications high power drives high voltage power supplies static switches voltage ratings part and ordering number repetitive peak voltages v drm and v rrm v conditions dcr1910v85* dcr1910v80 dcr1910v75 dcr1910v70 8500 8000 7500 7000 t vj = -40c to 125c, i drm = i rrm = 300ma, v drm , v rrm t p = 10ms, v dsm & v rsm = v drm & v rrm + 100v respectively lower voltage grades available. * 8200v @ -40 0 c, 8500v @ 0 0 c ordering information when ordering, select the required part number shown in the voltage ratings selection table. for example: dcr1910v85 note: please use the complete part number when orde ring and quote this number in any future correspondence relating to your order. key parameters v drm 8500v i t(av) 1910a i tsm 25000a dv/dt* 1500v/s di/dt 300a/s * higher dv/dt selections available outline type code: v (see package details for further information) fig. 1 package outline
semiconductor dcr1910v85 2/10 www.dynexsemi.com current ratings t case = 60c unless stated otherwise symbol parameter test conditions max. units double side cooled i t(av) mean on-state current half wave resistive load 1910 a i t(rms) rms value - 3000 a i t continuous (direct) on-state current - 2975 a surge ratings symbol parameter test conditions max. units i tsm surge (non-repetitive) on-state current 10ms half si ne, t case = 125c 25.0 ka i 2 t i 2 t for fusing v r = 0 3.125 ma 2 s thermal and mechanical ratings symbol parameter test conditions min. max. units r th(j-c) thermal resistance ? junction to case double side co oled dc - 0.00746 c/w single side cooled anode dc - 0.0130 c/w cathode dc - 0.0178 c/w r th(c-h) thermal resistance ? case to heatsink clamping force 54.0kn double side - 0.002 c/w (with mounting compound) single side - 0.004 c/w t vj virtual junction temperature on-state (conducting) - 1 35 c reverse (blocking) - 125 c t stg storage temperature range -55 125 c f m clamping force 48 59 kn
semiconductor dcr1910v85 3/10 www.dynexsemi.com dynamic characteristics symbol parameter test conditions min. max. units i rrm /i drm peak reverse and off-state current at v rrm /v drm , t case = 125c - 300 ma dv/dt max. linear rate of rise of off-state voltage t o 67% v drm , t j = 125c, gate open - 1500 v/s di/dt rate of rise of on-state current from 67% v drm to 2x i t(av) repetitive 50hz - 150 a/s gate source 30v, 10 , non-repetitive - 300 a/s t r < 0.5s, t j = 125c v t(to) threshold voltage ? low level 100a to1000a at t case = 125c - 0.9 v threshold voltage ? high level 1000a to 7200a at t case = 125c - 1.3 v r t on-state slope resistance ? low level 100a to 1000a at t case = 125c - 0.888 m on-state slope resistance ? high level 1000a to 7200 a at t case = 125c - 0.55 m t gd delay time v d = 67% v drm , gate source 30v, 10 - 3 s t r = 0.5s, t j = 25c t q turn-off time t j = 125c, v r = 200v, di/dt = 1a/s, - 1200 s dv dr /dt = 20v/s linear q s stored charge i t = 2000a, t j = 125c, di/dt ? 1a/s, 4800 8000 c i l latching current t j = 25c, v d = 5v - 3 a i h holding current t j = 25c, r g-k = , i tm = 500a, i t = 5a - 300 ma
semiconductor dcr1910v85 4/10 www.dynexsemi.com gate trigger characteristics and ratings symbol parameter test conditions max. units v gt gate trigger voltage v drm = 5v, t case = 25c 1.5 v v gd gate non-trigger voltage at 50% v drm, t case = 125c 0.4 v i gt gate trigger current v drm = 5v, t case = 25c 250 ma i gd gate non-trigger current at 50% v drm, t case = 125c 15 ma curves 0 1000 2000 3000 4000 5000 6000 7000 0.0 2.0 4.0 6.0 instantaneous on-state voltage v t - (v) instantaneous on-state current i t - (a) min 125c max 125c min 25c max 25c fig.2 maximum & minimum on-state characteristics v tm equation where a = 0.398265 b = 0.121095 v tm = a + bln (i t ) + c.i t +d. i t c = 0.000524 d = -0.000007 these values are valid for t j = 125c for i t 500a to 7200a
semiconductor dcr1910v85 5/10 www.dynexsemi.com 0 1 2 3 4 5 6 7 8 9 10 0 500 1000 1500 2000 2500 mean on-state current, i t(av) - (a) mean power dissipation - (kw) 180 120 90 60 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 1000 2000 3000 mean on-state current, i t(av) - (a) maximum case temperature, t case ( o c ) 180 120 90 60 30 fig.3 on-state power dissipation ? sine wave fig.4 m aximum permissible case temperature, double side cooled ? sine wave 0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 500 1000 1500 2000 2500 mean on-state current, i t(av) - (a) maximum heatsink temperature, t heatsink - ( o c ) 180 120 90 60 30 0 1 2 3 4 5 6 7 8 9 10 11 12 0 500 1000 1500 2000 2500 3000 3500 mean on-state current, i t(av) - (a) mean power dissipation - (kw) d.c. 180 120 90 60 30 fig.5 maximum permissible heatsink temperature, double side cooled ? sine wave fig.6 on-state power dissipation ? rectangular wav e
semiconductor dcr1910v85 6/10 www.dynexsemi.com 0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 500 1000 1500 2000 2500 3000 3500 4000 4500 mean on-state current, i t(av) - (a) maximum permissible case temperature ,t case -( c) d.c. 180 120 90 60 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 500 1000 1500 2000 2500 3000 3500 4000 mean on-state current, i t(av ) - (a) maximum heatsink temperature t heatsink -( o c) d.c. 180 120 90 60 30 fig.7 maximum permissible case temperature, double side cooled ? rectangular wave fig.8 maximum permissible heatsink temperature, double side cooled ? rectangular wave 0 2 4 6 8 10 12 14 16 18 20 0.001 0.01 0.1 1 10 100 time ( s ) thermal impedance , z th(j-c) - ( c/kw) double side cooling anode side cooling cathode sided cooling 1 2 3 4 double side cooled r i (c/kw) 0.9206 1.8299 3.4022 1.3044 t i (s) 0.0076807 0.0579454 0.4078613 1.2085 anode side cooled r i (c/kw) 0.9032 1.6719 3.0101 7.4269 t i (s) 0.0075871 0.0536531 0.3144537 5.624 cathode side cooled r i (c/kw) 0.9478 2.0661 1.6884 13.0847 t i (s) 0.0078442 0.0645541 0.3894389 4.1447 z th = [r i x ( 1-exp. (t/t i ))] [1] r th(j-c) conduction tables show the increments of thermal resistance r th(j-c) when the device operates at conduction angles other than d.c. double side cooling anode side cooling cathode sided cooling z th (z) z th (z) z th (z) sine. rect. sine. rect. sine. rect. 180 1.34 0.88 180 1.34 0.88 180 1.33 0.88 120 1.57 1.30 120 1.57 1.30 120 1.57 1.29 90 1.83 1.54 90 1.84 1.54 90 1.83 1.53 60 2.08 1.81 60 2.08 1.81 60 2.07 1.80 30 2.27 2.11 30 2.28 2.11 30 2.26 2.10 15 2.36 2.28 15 2.37 2.28 15 2.35 2.26 fig.9 maximum (limit) transient thermal impedance ? junction to case (c/kw)
semiconductor dcr1910v85 7/10 www.dynexsemi.com 10 15 20 25 1 10 100 number of cycles surge current, i tsm - (ka) conditions: tcase = 125c v r =0 pulse width = 10ms 0 10 20 30 40 50 60 70 1 10 100 pulse width, t p - (ms) surge current, i tsm - (ka) 0 1 2 3 4 5 6 i 2 t (ma 2 s) i 2 t i tsm conditions: t case = 125c v r = 0 half-sine wave fig.10 multi-cycle surge current fig.11 single-cycle surge current 0 5000 10000 15000 20000 25000 30000 0 5 10 15 20 25 rate of decay of on-state current, di/dt - (a/us) stored charge, qs - (uc) q smax = 7040.5*(di/dt) 0.4578 q smin = 4916.3*(di/dt) 0.5041 conditions: tj = 125 o c, v rpeak ~ 5100v v rm ~ 3400v snubber as appropriate to control reverse voltages 0 100 200 300 400 500 600 0 5 10 15 20 25 rate of decay of on-state current, di/dt - (a/us) reverse receovery current, i rr - (a) i rrmax = 63.4*(di/dt) 0.6984 i rrmin = 51.3*(di/dt) 0.7453 conditions: tj = 125 o c, v rpeak ~ 5100v v rm ~ 3400v snubber as appropriate to control reverse votages fig.12 stored charge fig.13 reverse recovery current
semiconductor dcr1910v85 8/10 www.dynexsemi.com 0 1 2 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 gate trigger current i gt , - (a) gate trigger voltage, v gt - (v) tj = 125 o c tj = 25 o c tj = -40 o c preferred gate drive area upper limit lower limit fig14 gate characteristics 0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 8 9 10 gate trigger current, i gt - (a) gate trigger voltage, v gt - (v) lower limit upper limit 5w 10w 20w 50w 100w 150w -40c fig. 15 gate characteristics 50 100 400 100 150 150 150 200 150 150 125 500 150 150 100 1000 150 100 25 10000 20 - - pulse width us frequency hz pulse power p gm (watts)
semiconductor dcr1910v85 9/10 www.dynexsemi.com package details for further package information, please contact cus tomer services. all dimensions in mm, unless state d otherwise. do not scale. anode cathode gate hole ?3.60 x 2.00 deep (in both electrodes) ? 1 . 5 3rd angle projection if in doubt ask do not scale 20 offset (nom.) to gate tube ?110.0 max. ?73.0 nom. ?73.0 nom. for package height see table device maximum thickness (mm) minimum thickness (mm) dcr1474sv18 27.265 26.515 dcr1475sv28 27.34 26.59 dcr1476sv42 27.57 26.82 dcr1478sv48 27.69 26.94 dcr1574sv28 27.34 26.59 dcr1575sv42 27.57 26.82 dcr1576sv52 27.69 26.94 dcr4060v22 27.265 26.515 dcr3780v28 27.34 26.59 dcr3030v42 27.57 26.82 dcr2720v52 27.69 26.94 dcr2290v65 27.95 27.2 dcr1910v85 28.31 27.56 lead length: 420mm lead terminal connector: m4 ring package outline type code: v fig.16 package outline
semiconductor dcr1910v85 10/10 www.dynexsemi.com power assembly capability the power assembly group was set up to provide a su pport service for those customers requiring more th an the basic semiconductor, and has developed a flexible range o f heatsink and clamping systems in line with advanc es in device voltages and current capability of our semiconductors. we offer an extensive range of air and liquid coole d assemblies covering the full range of circuit des igns in general use today. the assembly group offers high quality engineering support dedicated to designing new units to satisfy the growing needs of our customers. using the latest cad methods our team of design and applications engineers aim to provide the power as sembly complete solution (pacs). heatsinks the power assembly group has its own proprietary ra nge of extruded aluminium heatsinks which have been designed to optimise the performance of dynex semiconductors. data with respect to air natural, forced air and liquid cool ing (with flow rates) is available on request. for further information on device clamps, heatsinks and assemblies, please contact your nearest sales representative or customer services. stresses above those listed in this data sheet may cause permanent damage to the device. in extreme c onditions, as with all semiconductors, this may include potentially hazard ous rupture of the package. appropriate safety pre cautions should always be followed. http://www.dynexsemi.com e-mail: power_solutions@dynexsemi.com headquarters operations customer service dynex semiconductor ltd tel: +44(0)1522 502753 / 502901. fax: +44(0)1522 50 0020 doddington road, lincoln lincolnshire, ln6 3lf. united kingdom. tel: +44(0)1522 500500 fax: +44(0)1522 500550 dynex semiconductor 2003 technical documentation ? not for resale. produced in united kingdom. this publication is issued to provide information only wh ich (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form pa rt of any order or contract nor to be regarded as a representation relatin g to the products or services concerned. no warranty or gu arantee express or implied is made regarding the capab ility, performance or suitability of any product or service. the company reserv es the right to alter without prior notice the specif ication, design or price of any product or service. in formation concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility to fully determine the performance and suitability of any e quipment using such information and to ensure that any p ublication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant inj ury or death to the user. all products and materials ar e sold and services provided subject to the company?s conditions of sale, which are ava ilable on request. all brand names and product names used in this publicatio n are trademarks, registered trademarks or trade names of their respective owners.
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